Built-in test for VLSI : pseudorandom techniques

This handbook provides ready access to all of the major concepts, techniques, problems and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. The main intention of this book is to present the material in a unified manner, making it a useful source for practising professionals and students alike. It opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, reviewing by comparison the principles of design for testability of more advanced digital technology. It then offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing; and various data compression methods, such as polynomial dividers and unique shift-register sequence generators with special applications. Also detailed are random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing. The last section describes the kinds of test support systems necessary for a successful built-in test.