A Guide to VHDL Syntax

A reference for anyone writing VHDL models or using VHDL in CAD development. VHDL is clearly becoming the defacto standard as an electronic hardware description language yet the bible of VHDL, the large and complex Language Reference Manual (LRM), is exceptionally cumbersome, if not difficult, to use various parts of the syntax for major constructs are spread in disparate sections throughout the Manual. Designed to alleviate such problems and frustrations, this guide describes the complete syntax of the IEEE Std 1076-1993 version of VHDL showing the complete syntax of major VHDL constructs and sub-constructs in an easy-to-read manner, with clear examples of each.