Test Set Compaction and Diagnosis of Crosstalk Faults

DSM chips have increasingly started to suffer from signal integrity faults as the feature sizes continue to shrink and operating frequencies increases to multi-GHz range. Crosstalk faults are the major source of all signal integrity problems. These noise effects are caused by parasitic couplings between neighboring wires and may lead to change in signal logic levels or may add significant signal delays. Crosstalk faults, therefore, need to be tested to avoid any possible system failures. Due to the various possible crosstalk faults and potential victim wires the test set obtained is enormous. Therefore, it needs to be reduced in order to meet the storage and test time requirements. Additionally, once a circuit is identified as defective the possible source of defect needs to be located to avoid future circuit failures. If the possible source of defect is a crosstalk fault corrective actions are required in the physical design to increase yield and reliability of the circuit. In this thesis all the above stated problems related to crosstalk faults are addressed. The major contribution of this work can be classified into three sections:Crosstalk noise analysis: In order to determine the accurate crosstalk noise effects interconnects are modeled into distributed RLGC components and SPICE simulations are performed. But usually this process is time consuming and therefore analytical models are preferred. In this work three different analytical models are derived which have not been discussed before in literature for determining crosstalk induced noise and delay effects. The results are compared with equivalent PSPICE models which confirms the accuracy of these much faster analytical interconnect models.Crosstalk test set generation and its compaction: To ensure low failure rates circuits need to be tested for maximum possible coupling noise effects. For this a new method for generating crosstalk test patterns is proposed and implemented which takes into account all the possible spatial, temporal and functional characteristics of the design. A set of test vectors are generated for each possible victim wire, using a modified stuck-at fault ATPG, by exciting maximum possible influencing aggressors. Thereafter, the test set is compacted using a novel fault chaining algorithm. In the end, four different variations ofthis proposed algorithm are implemented and analyzed.Crosstalk fault diagnosis: In this work a new method is proposed and implemented to locate the victim wires and the type of crosstalk fault after a faulty response is obtained on the primary output(s). The compacted test patterns are used in the diagnostic process to show the effectiveness of the approach. Initially, stuck-at fault simulations are performed to identify probable crosstalk faults. Next, by considering the circuit's structure some of these faults are removed. Lastly, by considering the aggressor states and their strengths the final shortlisted suspects list is obtained.