Parametric Reliability of 6T-SRAM Core Cell Arrays

The increasing integration density of microelectronic circuits results in aging mechanisms, some of them shifting the parameters of MOS transistors during lifetime. This work focuses on the impact of these parametrical degradation mechanisms on Static Random Access Memory (SRAM) arrays. First, the impact of each effect on single SRAM cells was simulated. Because of presently non-sufficient simulation models, these results had to be confirmed and completed by measurements. By using novel measurement techniques which were developed within this work, the impact of the worst effect on large-scale SRAM arrays could be examined for the first time. The most critical scenarios during lifetime could be identified. Finally, a comparison of known countermeasures was performed in order to choose the most promising methods.