CMOS Lna Design for GSM Applications : Low Noise Amplifier Designing in 0.35µm CMOS Technology for 900MHz Applications

Increasing demand of wireless communication systems motivated us to study the feasibility of transceiver circuits in CMOS technology for the implementation of RF and microwave circuits. The advance in the CMOS technology has become attractive due to the possibility of integrating the whole system on a single chip. The rapid progress in CMOS scaling technology has put standard CMOS processes in a favorable role in RF circuit fabrication. This work focuses on the design of a Low Noise Amplifier (LNA) in TSMC 0.35m CMOS technology for 900MHz applications. A single ended cascade configuration with inductive degeneration followed by a common source configuration is used. The circuit is designed in Cadence and employs feedback technique along with the use of a PMOS as a feed forward distortion canceller to further improve linearity. At 900 MHz, the LNA has a gain of 10.48dB, noise figure of 3.3dB, input referred P1dB of -1.81 dBm, output referred P1dB of 7.63dBm, IIP3 of +12.8dBm and OIP3 of +23.22dBm consuming 26mA from 1.5V supply. This design has the best input referred P1dB reported till date in 0.35 m CMOS technology for the desired frequency of operation.