Self-Modifying Circuitry for Trillion-Element Reconfigurable Devices : An analysis of a future computing paradigm for efficient, scalable, defect-tolerant processing

As transistors density continues to rise, it becomes increasingly difficult to scale current computing designs to utilize these high transistor counts. This work presents a scalable alternative to the traditional von Neumann architecture, in the form of a self-configurable array of programmable elements. Unlike traditional FPGAs, this architecture utilizes self-analysis and self-modification to address a number of scalability challenges, including handling mixed-granularity designs; handling of defects; and dynamic architecture tuning. Included are details of the basic architecture, examples of its application to solving real-world problems, and an analysis of its scalability. Emphasis is placed on the ability of the system's self-configuration mechanism to support efficient parallel bootstrapping of the system. This work also discusses the three-dimensional version of the Cell Matrix, and explores how this extra dimension can be used to more-efficiently solve future problems.